Architecture >> SspLowSpeedDecoderReg::mapping

Processes
comb	( deserRst , dlyConfig , eyeWidth , idleCode , r , readMaster , statusCnt , statusOut , writeMaster )
seq	( deserClk )
comb	( deserRst , dlyConfig , eyeWidth , idleCode , r , readMaster , statusCnt , statusOut , writeMaster )
seq	( deserClk )

Constants
STATUS_SIZE_C	*positive := 3 NUM_LANE_G**
STATUS_WIDTH_C	positive := 16
REG_INIT_C	RegType := ( enUsrDlyCfg = > ite ( SIMULATION_G , ' 1 ' , ' 0 ' ) , usrDlyCfg = > ( others = > toSlv ( 219 , 9 ) ) , minEyeWidth = > toSlv ( 80 , 8 ) , lockingCntCfg = > ite ( SIMULATION_G , x " 00_0004 " , x " 00_FFFF " ) , bypFirstBerDet = > ' 1 ' , polarity = > ( others = > ' 0 ' ) , bitOrder = > ( others = > ' 0 ' ) , errorMask = > ( others = > ' 0 ' ) , lockOnIdle = > ' 0 ' , cntRst = > ' 1 ' , rollOverEn = > ( others = > ' 0 ' ) , readSlave = > AXI_LITE_READ_SLAVE_INIT_C , writeSlave = > AXI_LITE_WRITE_SLAVE_INIT_C )

Signals
r	RegType := REG_INIT_C
rin	RegType
statusIn	slv ( STATUS_SIZE_C- 1 downto 0 )
statusOut	slv ( STATUS_SIZE_C- 1 downto 0 )
statusCnt	SlVectorArray ( STATUS_SIZE_C- 1 downto 0 , STATUS_WIDTH_C- 1 downto 0 )
readMaster	AxiLiteReadMasterType
readSlave	AxiLiteReadSlaveType
writeMaster	AxiLiteWriteMasterType
writeSlave	AxiLiteWriteSlaveType

Records
RegType

Instantiations
u_axiliteasync	AxiLiteAsync <Entity AxiLiteAsync>
u_syncstatusvector	SyncStatusVector <Entity SyncStatusVector>
u_axiliteasync	AxiLiteAsync <Entity AxiLiteAsync>
u_syncstatusvector	SyncStatusVector <Entity SyncStatusVector>

The documentation for this design unit was generated from the following files:

Processes

Constants