Ssp10b12bTb.tb Architecture Reference

Architecture >> Ssp10b12bTb::tb

Processes
gen
check
gen
check

Constants
TPD_G	time := 1 ns
RST_POLARITY_G	sl := ' 0 '
RST_ASYNC_G	boolean := true
AUTO_FRAME_G	boolean := true

Signals
clk	sl
rst	sl := RST_POLARITY_G
encValid	sl := ' 0 '
encSof	sl := ' 0 '
encEof	sl := ' 0 '
encDataIn	slv ( 9 downto 0 )
encDataOut	slv ( 11 downto 0 )
decDataIn	slv ( 11 downto 0 )
decDataOut	slv ( 9 downto 0 )
decValid	sl
decSof	sl
decEof	sl
decEofe	sl
decCodeError	sl
decDispError	sl
validInt	sl

Instantiations
u_sspencoder10b12b	SspEncoder10b12b <Entity SspEncoder10b12b>
u_sspdecoder10b12b_1	SspDecoder10b12b <Entity SspDecoder10b12b>
u_clkrst_1	ClkRst <Entity ClkRst>
u_sspencoder10b12b	SspEncoder10b12b <Entity SspEncoder10b12b>
u_sspdecoder10b12b_1	SspDecoder10b12b <Entity SspDecoder10b12b>
u_clkrst_1	ClkRst <Entity ClkRst>

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The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/Ssp10b12bTb.vhd
• protocols/ssp/tb/Ssp10b12bTb.vhd