SsiPrbsRateGen Entity Reference

Inheritance diagram for SsiPrbsRateGen:

Collaboration diagram for SsiPrbsRateGen:

Entities
SsiPrbsRateGen.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_unsigned
std_logic_arith
StdRtlPkg	Package <StdRtlPkg>
AxiLitePkg	Package <AxiLitePkg>
AxiStreamPkg	Package <AxiStreamPkg>
SsiPkg	Package <SsiPkg>

Generics
TPD_G	time := 1 ns
RST_ASYNC_G	boolean := false
VALID_THOLD_G	integer range 0 to ( 2 ** 24 ) := 1
VALID_BURST_MODE_G	boolean := false
MEMORY_TYPE_G	string := " block "
CASCADE_SIZE_G	natural range 1 to ( 2 ** 24 ) := 1
FIFO_ADDR_WIDTH_G	natural range 4 to 48 := 9
FIFO_INT_WIDTH_SELECT_G	string := " WIDE "
PRBS_SEED_SIZE_G	natural range 32 to 512 := 32
PRBS_FIFO_PIPE_STAGES_G	integer range 0 to 16 := 0
AXIS_CLK_FREQ_G	real := 156 . 25E + 6
AXIS_CONFIG_G	AxiStreamConfigType
USE_AXIL_CLK_G	boolean := false

Ports
mAxisClk	in	sl
mAxisRst	in	sl
mAxisMaster	out	AxiStreamMasterType
mAxisSlave	in	AxiStreamSlaveType
axilClk	in	sl := ' 0 '
axilRst	in	sl := ' 0 '
axilReadMaster	in	AxiLiteReadMasterType
axilReadSlave	out	AxiLiteReadSlaveType
axilWriteMaster	in	AxiLiteWriteMasterType
axilWriteSlave	out	AxiLiteWriteSlaveType

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The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/SsiPrbsRateGen.vhd
• protocols/ssi/rtl/SsiPrbsRateGen.vhd