SsiFilterTb.testbed Architecture Reference

Architecture >> SsiFilterTb::testbed

Processes
comb	( r , slowRst )
seq	( slowClk )
PROCESS_167	( fastClk )
PROCESS_168	( failedDly , passedDly )
comb	( r , slowRst )
seq	( slowClk )
PROCESS_379	( fastClk )
PROCESS_380	( failedDly , passedDly )

Constants
SLOW_CLK_PERIOD_C	time := 6 . 4 ns
FAST_CLK_PERIOD_C	time := 5 ns
TPD_C	time := ( FAST_CLK_PERIOD_C/ 4 )
SLAVE_AXI_CONFIG_C	AxiStreamConfigType := ssiAxiStreamConfig ( 16 )
MASTER_AXI_CONFIG_C	AxiStreamConfigType := ssiAxiStreamConfig ( 8 )
REG_INIT_C	RegType := ( passed = > ' 0 ' , toggle = > ' 0 ' , flood = > ' 1 ' , floodCnt = > x " 0000 " , movCnt = > 0 , sAxisMaster = > AXI_STREAM_MASTER_INIT_C )

Signals
r	RegType := REG_INIT_C
rin	RegType
slowClk	sl := ' 0 '
slowRst	sl := ' 1 '
fastClk	sl := ' 0 '
fastRst	sl := ' 1 '
failed	sl := ' 0 '
failedDly	sl := ' 0 '
passedDly	sl := ' 0 '
mAxisMaster	AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C

Records
RegType

Instantiations
clkrst_fast	ClkRst <Entity ClkRst>
clkrst_slow	ClkRst <Entity ClkRst>
u_fifo	SsiFifo <Entity SsiFifo>
clkrst_fast	ClkRst <Entity ClkRst>
clkrst_slow	ClkRst <Entity ClkRst>
u_fifo	SsiFifo <Entity SsiFifo>

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The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/SsiFilterTb.vhd
• protocols/ssi/tb/SsiFilterTb.vhd