SsiCmdMaster.rtl Architecture Reference

Architecture >> SsiCmdMaster::rtl

Processes
comb	( cmdRst , fifoAxisMaster , r )
seq	( cmdClk , cmdRst )
comb	( cmdRst , fifoAxisMaster , r )
seq	( cmdClk , cmdRst )

Constants
REG_INIT_C	RegType := ( txnNumber = > ( others = > ' 0 ' ) , cmdMaster = > SSI_CMD_MASTER_INIT_C )
INT_CONFIG_C	AxiStreamConfigType := ssiAxiStreamConfig ( 4 )

Types
StateType	( IDLE_S , CMD_S , DUMP_S )

Signals
fifoAxisMaster	AxiStreamMasterType
fifoAxisSlave	AxiStreamSlaveType
r	RegType := REG_INIT_C
rin	RegType

Records
RegType

Instantiations
slaveaxistreamfifo	AxiStreamFifoV2 <Entity AxiStreamFifoV2>
slaveaxistreamfifo	AxiStreamFifoV2 <Entity AxiStreamFifoV2>

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The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/SsiCmdMaster.vhd
• protocols/ssi/rtl/SsiCmdMaster.vhd