SlvFixedDelay.rtl Architecture Reference

Architecture >> SlvFixedDelay::rtl

Processes
comb	( din , r )
seq	( clk )
comb	( din , r )
seq	( clk )

Constants
REG_INIT_C	RegType := ( shift = > ( others = > ( others = > ' 0 ' ) ) )

Types
VectorArray	( DELAY_G downto 0 ) slv ( WIDTH_G- 1 downto 0 )

Signals
r	RegType := REG_INIT_C
rin	RegType

Attributes
srl_style	string
srl_style	signal is DELAY_STYLE_G

Records
RegType

Instantiations
u_srl16_delay	Srl16Delay <Entity Srl16Delay>
u_ram_delay	LutFixedDelay <Entity LutFixedDelay>
u_srl16_delay	Srl16Delay <Entity Srl16Delay>
u_ram_delay	LutFixedDelay <Entity LutFixedDelay>

---

The documentation for this design unit was generated from the following files:

• base/delay/rtl/SlvFixedDelay.vhd
• build/SRC_VHDL/surf/SlvFixedDelay.vhd