LutFixedDelay Entity Reference

Inheritance diagram for LutFixedDelay:

Collaboration diagram for LutFixedDelay:

Entities
LutFixedDelay.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
numeric_std
math_real
StdRtlPkg	Package <StdRtlPkg>

Generics
TPD_G	time := 1 ns
XIL_DEVICE_G	string := " ULTRASCALE_PLUS "
DELAY_G	natural range 33 to 513 := 256
WIDTH_G	positive := 16

Ports
clk	in	sl
din	in	slv ( WIDTH_G- 1 downto 0 )
dout	out	slv ( WIDTH_G- 1 downto 0 )

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The documentation for this design unit was generated from the following files:

• base/delay/rtl/LutFixedDelay.vhd
• build/SRC_VHDL/surf/LutFixedDelay.vhd