LutFixedDelay.rtl Architecture Reference

Architecture >> LutFixedDelay::rtl

Processes
comb	( r )
seq	( clk )
comb	( r )
seq	( clk )

Constants
DELAY_C	integer := DELAY_G- 1
ADDR_BITS_C	integer := log2 ( DELAY_C )
REG_INIT_C	RegType := ( addr = > ( others = > ' 0 ' ) )

Signals
r	RegType := REG_INIT_C
rin	RegType
q	slv ( WIDTH_G- 1 downto 0 ) := ( others = > ' 0 ' )
addra	slv ( ADDR_BITS_C- 1 downto 0 )

Records
RegType

Instantiations
u_ram_prim	SinglePortRamPrimitive <Entity SinglePortRamPrimitive>
u_ram_prim	SinglePortRamPrimitive <Entity SinglePortRamPrimitive>

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The documentation for this design unit was generated from the following files:

• base/delay/rtl/LutFixedDelay.vhd
• build/SRC_VHDL/surf/LutFixedDelay.vhd