SinglePortRamPrimitive Entity Reference

Inheritance diagram for SinglePortRamPrimitive:

Entities
SinglePortRamPrimitive.mapping	architecture
SinglePortRamPrimitive.rtl	architecture

Libraries
ieee
surf
unisim

Use Clauses
std_logic_1164
StdRtlPkg	Package <StdRtlPkg>
vcomponents

Generics
TPD_G	time := 1 ns
XIL_DEVICE_G	string := " ULTRASCALE_PLUS "
DEPTH_G	integer range 1 to 512 := 64
WIDTH_G	positive := 16

Ports
clk	in	sl := ' 0 '
we	in	sl := ' 1 '
addr	in	slv ( log2 ( DEPTH_G ) - 1 downto 0 ) := ( others = > ' 0 ' )
din	in	slv ( WIDTH_G- 1 downto 0 ) := ( others = > ' 0 ' )
dout	out	slv ( WIDTH_G- 1 downto 0 ) := ( others = > ' 0 ' )

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The documentation for this design unit was generated from the following files:

• base/ram/dummy/SinglePortRamPrimitiveDummy.vhd
• base/ram/xilinx/SinglePortRamPrimitive.vhd
• build/SRC_VHDL/surf/SinglePortRamPrimitiveDummy.vhd