SinglePortRamPrimitive.rtl Architecture Reference

Architecture >> SinglePortRamPrimitive::rtl

Processes
seq	( clk )

Constants
INIT_C	bit_vector ( 511 downto 0 ) := ( others = > ' 0 ' )

Signals
q	slv ( WIDTH_G- 1 downto 0 ) := ( others = > ' 0 ' )

Instantiations
lut32	ram32x1s
lut64	ram64x1s
lut128	ram128x1s
lut256	ram256x1s
lut512	ram512x1s

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The documentation for this design unit was generated from the following file:

• base/ram/xilinx/SinglePortRamPrimitive.vhd