Srl16Delay Entity Reference

Inheritance diagram for Srl16Delay:

Entities
Srl16Delay.mapping	architecture
Srl16Delay.rtl	architecture

Libraries
ieee
surf
unisim

Use Clauses
std_logic_1164
StdRtlPkg	Package <StdRtlPkg>
vcomponents

Generics
TPD_G	time := 1 ns
XIL_DEVICE_G	string := " ULTRASCALE_PLUS "
DELAY_G	natural range 3 to 17 := 3
WIDTH_G	positive := 16

Ports
clk	in	sl := ' 0 '
din	in	slv ( WIDTH_G- 1 downto 0 ) := ( others = > ' 0 ' )
dout	out	slv ( WIDTH_G- 1 downto 0 ) := ( others = > ' 0 ' )
dly_2	in	slv ( 3 downto 0 ) := toSlv ( DELAY_G- 2 , 4 )

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The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/Srl16DelayDummy.vhd
• xilinx/dummy/Srl16DelayDummy.vhd
• xilinx/general/rtl/Srl16Delay.vhd