Srl16Delay.rtl Architecture Reference

Architecture >> Srl16Delay::rtl

Processes
seq	( clk )

Signals
q	slv ( WIDTH_G- 1 downto 0 )

Attributes
rloc	string
rloc	label is " X0Y " & integer ' image ( i/ 8 )
rloc	label is " X0Y " & integer ' image ( i/ 16 )

Instantiations
shift_reg	srl16e
shift_reg	srl16e

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The documentation for this design unit was generated from the following file:

• xilinx/general/rtl/Srl16Delay.vhd