SlvDelayRamTb.testbed Architecture Reference

Architecture >> SlvDelayRamTb::testbed

Processes
comb	( dout , r , rst )
seq	( clk )
PROCESS_27	( clk )

Constants
CLK_PERIOD_C	time := 4 ns
TPD_C	time := CLK_PERIOD_C/ 4
WIDTH_C	integer := 16
MAX_DELAY_C	integer := 514
DELAY_C	integer := MAX_DELAY_C
DO_REG_C	boolean := true
MEMORY_TYPE_C	string := " block "
MAX_COUNT_BITS_C	integer := log2 ( MAX_DELAY_C- ite ( DO_REG_C , 2 , 1 ) )
MAX_COUNT_C	integer := DELAY_C- ite ( DO_REG_C , 3 , 2 )
REG_INIT_C	RegType := ( passed = > ' 0 ' , failed = > ' 0 ' , count = > 0 , countDelay = > ( others = > 0 ) )

Types
CountDelayType	( MAX_DELAY_C- 1 downto 0 ) integer range 0 to ( 2 ** WIDTH_C- 1 )

Signals
r	RegType := REG_INIT_C
rin	RegType
clk	sl := ' 0 '
rst	sl := ' 1 '
din	slv ( WIDTH_C- 1 downto 0 ) := ( others = > ' 0 ' )
dout	slv ( WIDTH_C- 1 downto 0 ) := ( others = > ' 0 ' )
maxCount	slv ( MAX_COUNT_BITS_C- 1 downto 0 ) := toSlv ( MAX_COUNT_C , MAX_COUNT_BITS_C )
passed	sl := ' 0 '
failed	sl := ' 0 '

Records
RegType

Instantiations
u_clkrst	ClkRst <Entity ClkRst>
u_slvdelayram	SlvDelayRam <Entity SlvDelayRam>

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The documentation for this design unit was generated from the following file:

• base/delay/tb/SlvDelayRamTb.vhd