SlvDelayRam Entity Reference

Inheritance diagram for SlvDelayRam:

Entities
SlvDelayRam.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_unsigned
numeric_std
StdRtlPkg	Package <StdRtlPkg>

Generics
TPD_G	time := 1 ns
RST_POLARITY_G	sl := ' 1 '
MEMORY_TYPE_G	string := " block "
DO_REG_G	boolean := true
DELAY_G	integer range 3 to ( 2 ** 24 ) := 3
WIDTH_G	positive := 1

Ports
clk	in	sl
rst	in	sl := not ( RST_POLARITY_G )
en	in	sl := ' 1 '
maxCount	in	slv ( log2 ( DELAY_G- ite ( DO_REG_G , 2 , 1 ) ) - 1 downto 0 ) := toSlv ( DELAY_G- ite ( DO_REG_G , 3 , 2 ) , log2 ( DELAY_G- ite ( DO_REG_G , 2 , 1 ) ) )
din	in	slv ( WIDTH_G- 1 downto 0 )
dout	out	slv ( WIDTH_G- 1 downto 0 )

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The documentation for this design unit was generated from the following files:

• base/delay/rtl/SlvDelayRam.vhd
• build/SRC_VHDL/surf/SlvDelayRam.vhd