SlvDelayRam.rtl Architecture Reference

Architecture >> SlvDelayRam::rtl

Processes
comb	( doutInt , en , maxCount , r , rst )
seq	( clk )
MEM_PROC	( clk )
comb	( doutInt , en , maxCount , r , rst )
seq	( clk )
MEM_PROC	( clk )

Constants
XST_BRAM_STYLE_C	string := MEMORY_TYPE_G
INIT_C	slv ( WIDTH_G- 1 downto 0 ) := slvZero ( WIDTH_G )
REG_INIT_C	RegType := ( addr = > 0 , maxCount = > 0 , doutReg = > INIT_C )

Types
MemType	( DELAY_G- 1 - ite ( DO_REG_G , 2 , 1 ) downto 0 ) slv ( WIDTH_G- 1 downto 0 )

Signals
mem	MemType := ( others = > ( others = > ' 0 ' ) )
r	RegType := REG_INIT_C
rin	RegType
doutInt	slv ( WIDTH_G- 1 downto 0 )

Attributes
ram_style	string
ram_style	signal is XST_BRAM_STYLE_C
ram_extract	string
ram_extract	signal is " TRUE "
syn_ramstyle	string
syn_ramstyle	signal is XST_BRAM_STYLE_C
syn_keep	string
syn_keep	signal is " TRUE "

Records
RegType

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The documentation for this design unit was generated from the following files:

• base/delay/rtl/SlvDelayRam.vhd
• build/SRC_VHDL/surf/SlvDelayRam.vhd