SlvArraytoAxiLite.rtl Architecture Reference

Architecture >> SlvArraytoAxiLite::rtl

Processes
comb	( ack , axilRst , inSlv , r )
seq	( axilClk )
comb	( ack , axilRst , inSlv , r )
seq	( axilClk )

Constants
REG_INIT_C	RegType := ( cnt = > 0 , valid = > ( others = > ' 0 ' ) , inSlv = > ( others = > ( others = > ' 0 ' ) ) , req = > AXI_LITE_REQ_INIT_C , state = > IDLE_S )

Types
StateType	( IDLE_S , WAIT_S )

Signals
r	RegType := REG_INIT_C
rin	RegType
inSlv	Slv32Array ( SIZE_G- 1 downto 0 )
ack	AxiLiteAckType

Records
RegType

Instantiations
syncfifo	SynchronizerFifo <Entity SynchronizerFifo>
u_axilitemaster	AxiLiteMaster <Entity AxiLiteMaster>
syncfifo	SynchronizerFifo <Entity SynchronizerFifo>
u_axilitemaster	AxiLiteMaster <Entity AxiLiteMaster>

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The documentation for this design unit was generated from the following files:

• axi/bridge/rtl/SlvArraytoAxiLite.vhd
• build/SRC_VHDL/surf/SlvArraytoAxiLite.vhd