SlvArraytoAxiLite Entity Reference

Inheritance diagram for SlvArraytoAxiLite:

Collaboration diagram for SlvArraytoAxiLite:

Entities
SlvArraytoAxiLite.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_arith
std_logic_unsigned
StdRtlPkg	Package <StdRtlPkg>
AxiLitePkg	Package <AxiLitePkg>

Generics
TPD_G	time := 1 ns
COMMON_CLK_G	boolean := false
SIZE_G	positive := 1
ADDR_G	Slv32Array := ( 0 = > x " 00000000 " )

Ports
clk	in	sl
rst	in	sl
input	in	Slv32Array ( SIZE_G- 1 downto 0 )
axilClk	in	sl
axilRst	in	sl
axilReadMaster	out	AxiLiteReadMasterType
axilReadSlave	in	AxiLiteReadSlaveType
axilWriteMaster	out	AxiLiteWriteMasterType
axilWriteSlave	in	AxiLiteWriteSlaveType

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The documentation for this design unit was generated from the following files:

• axi/bridge/rtl/SlvArraytoAxiLite.vhd
• build/SRC_VHDL/surf/SlvArraytoAxiLite.vhd