Si5394I2cCore Entity Reference

Inheritance diagram for Si5394I2cCore:

Collaboration diagram for Si5394I2cCore:

Entities
Si5394I2cCore.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_arith
std_logic_unsigned
StdRtlPkg	Package <StdRtlPkg>
AxiLitePkg	Package <AxiLitePkg>
I2cPkg	Package <I2cPkg>

Generics
TPD_G	time := 1 ns
MEMORY_INIT_FILE_G	string := " none "
I2C_BASE_ADDR_G	slv ( 1 downto 0 ) := " 00 "
I2C_SCL_FREQ_G	real := 100 . 0E + 3
I2C_MIN_PULSE_G	real := 100 . 0E - 9
AXIL_CLK_FREQ_G	real := 156 . 25E + 6

Ports
i2ci	in	i2c_in_type
i2co	out	i2c_out_type
irqL	in	sl
lolL	in	sl
losL	in	sl
rstL	out	sl
booting	out	sl
axilReadMaster	in	AxiLiteReadMasterType
axilReadSlave	out	AxiLiteReadSlaveType
axilWriteMaster	in	AxiLiteWriteMasterType
axilWriteSlave	out	AxiLiteWriteSlaveType
axilClk	in	sl
axilRst	in	sl

---

The documentation for this design unit was generated from the following file:

• devices/Silabs/si5394/rtl/Si5394I2cCore.vhd