Architecture >> Si5394I2cCore::rtl

Processes
comb	( axilReadMaster , axilRst , axilWriteMaster , r , ramData , regOut )
seq	( axilClk )

Constants
BOOT_ROM_C	boolean := ( MEMORY_INIT_FILE_G/ = " none " )
I2C_SCL_5xFREQ_C	*real := 5 . 0 I2C_SCL_FREQ_G**
PRESCALE_C	natural := ( getTimeRatio ( AXIL_CLK_FREQ_G , I2C_SCL_5xFREQ_C ) ) - 1
FILTER_C	*natural := natural ( AXIL_CLK_FREQ_G I2C_MIN_PULSE_G ) + 1**
I2C_ADDR_C	slv ( 9 downto 0 ) := ( " 000 " & " 11010 " & I2C_BASE_ADDR_G )
TIMEOUT_CAL_C	natural := getTimeRatio ( 625 . 0E - 3 , ( 1 . 0 / AXIL_CLK_FREQ_G ) ) - 1
TIMEOUT_I2C_C	natural := getTimeRatio ( 10 . 00E - 6 , ( 1 . 0 / AXIL_CLK_FREQ_G ) ) - 1
MY_I2C_REG_MASTER_IN_INIT_C	I2cRegMasterInType := ( i2cAddr = > I2C_ADDR_C , tenbit = > ' 0 ' , regAddr = > ( others = > ' 0 ' ) , regWrData = > ( others = > ' 0 ' ) , regOp = > ' 0 ' , regAddrSkip = > ' 0 ' , regAddrSize = > " 00 " , regDataSize = > " 00 " , regReq = > ' 0 ' , busReq = > ' 0 ' , endianness = > ' 0 ' , repeatStart = > ' 0 ' , wrDataOnRd = > ' 0 ' )
REG_INIT_C	RegType := ( timer = > TIMEOUT_CAL_C , axiRd = > ' 0 ' , ramAddr = > ( others = > ' 0 ' ) , booting = > ite ( BOOT_ROM_C , ' 1 ' , ' 0 ' ) , data = > ( others = > ' 0 ' ) , addr = > ( others = > ' 0 ' ) , page = > ( others = > ' 0 ' ) , axilWriteSlave = > AXI_LITE_WRITE_SLAVE_INIT_C , axilReadSlave = > AXI_LITE_READ_SLAVE_INIT_C , regIn = > MY_I2C_REG_MASTER_IN_INIT_C , state = > POR_WAIT_S )

Types
StateType	( POR_WAIT_S , BOOT_ROM_S , IDLE_S , PAGE_REQ_S , PAGE_ACK_S , DATA_REQ_S , DATA_ACK_S )

Records
RegType

Instantiations
u_rom	SimpleDualPortRamXpm <Entity SimpleDualPortRamXpm>
u_i2cregmaster	I2cRegMaster <Entity I2cRegMaster>
u_rstl	PwrUpRst <Entity PwrUpRst>

The documentation for this design unit was generated from the following file:

Processes

Constants