Si5324.rtl Architecture Reference

Architecture >> Si5324::rtl

Processes
comb	( axilReadMaster , axilRst , axilWriteMaster , r , ramData , rdData , rdEn )
seq	( axilClk )

Constants
BOOT_ROM_C	boolean := ( MEMORY_INIT_FILE_G/ = " none " )
DLY_C	natural := 8 * integer ( SPI_SCLK_PERIOD_G/ CLK_PERIOD_G )
REG_INIT_C	RegType := ( axilRd = > ' 0 ' , wrEn = > ' 0 ' , wrData = > ( others = > ' 0 ' ) , data = > ( others = > ' 0 ' ) , addr = > ( others = > ' 0 ' ) , timer = > 0 , cnt = > 0 , wrArray = > ( others = > ( others = > ' 0 ' ) ) , axilWriteSlave = > AXI_LITE_WRITE_SLAVE_INIT_C , axilReadSlave = > AXI_LITE_READ_SLAVE_INIT_C , ramAddr = > ( others = > ' 0 ' ) , booting = > ite ( BOOT_ROM_C , ' 1 ' , ' 0 ' ) , state = > BOOT_ROM_S )

Types
StateType	( BOOT_ROM_S , IDLE_S , INIT_S , REQ_S , ACK_S , DONE_S )

Signals
r	RegType := REG_INIT_C
rin	RegType
freeRunClk	sl
rdEn	sl
rdData	slv ( 15 downto 0 )
ramData	slv ( 15 downto 0 ) := ( others = > ' 0 ' )

Records
RegType

Instantiations
u_rom	SimpleDualPortRamXpm <Entity SimpleDualPortRamXpm>
u_spimaster	SpiMaster <Entity SpiMaster>
u_obuft	obuft

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The documentation for this design unit was generated from the following file:

• devices/Silabs/si5324/rtl/Si5324.vhd