Si5324 Entity Reference

Inheritance diagram for Si5324:

Collaboration diagram for Si5324:

Entities
Si5324.rtl	architecture

Libraries
ieee
surf
unisim

Use Clauses
std_logic_1164
std_logic_arith
std_logic_unsigned
StdRtlPkg	Package <StdRtlPkg>
AxiLitePkg	Package <AxiLitePkg>
vcomponents

Generics
TPD_G	time := 1 ns
MEMORY_INIT_FILE_G	string := " none "
CLK_PERIOD_G	real := ( 1 . 0 / 156 . 25E + 6 )
SPI_SCLK_PERIOD_G	real := ( 1 . 0 / 5 . 0E + 6 )

Ports
axilClk	in	sl
axilRst	in	sl
axilReadMaster	in	AxiLiteReadMasterType
axilReadSlave	out	AxiLiteReadSlaveType
axilWriteMaster	in	AxiLiteWriteMasterType
axilWriteSlave	out	AxiLiteWriteSlaveType
booting	out	sl
rstL	out	sl
rate	out	slv ( 1 downto 0 )
cmode	out	sl
csL	out	sl
sclk	out	sl
mosi	out	sl
miso	in	sl

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The documentation for this design unit was generated from the following file:

• devices/Silabs/si5324/rtl/Si5324.vhd