SelectioDeser7Series.mapping Architecture Reference

Architecture >> SelectioDeser7Series::mapping

Signals
clkx4	sl := ' 0 '
clkx1	sl := ' 0 '
rstx1	sl := ' 1 '
rstx4	sl := ' 1 '

Instantiations
u_mmcm	ClockManager7 <Entity ClockManager7>
u_lane	SelectioDeserLane7Series <Entity SelectioDeserLane7Series>

---

The documentation for this design unit was generated from the following file:

• xilinx/7Series/general/rtl/SelectioDeser7Series.vhd