SelectioDeser7Series Entity Reference

Inheritance diagram for SelectioDeser7Series:

Collaboration diagram for SelectioDeser7Series:

Entities
SelectioDeser7Series.mapping	architecture

Libraries
ieee
surf
unisim

Use Clauses
std_logic_1164
std_logic_arith
std_logic_unsigned
StdRtlPkg	Package <StdRtlPkg>
AxiLitePkg	Package <AxiLitePkg>
vcomponents

Generics
TPD_G	time := 1 ns
SIMULATION_G	boolean := false
NUM_LANE_G	positive := 1
IODELAY_GROUP_G	string := " DESER_GROUP "
REF_FREQ_G	real := 300 . 0
INPUT_BUFG_G	boolean := false
FB_BUFG_G	boolean := false
CLKIN_PERIOD_G	real := 10 . 0
DIVCLK_DIVIDE_G	positive := 1
CLKFBOUT_MULT_G	positive := 10
CLKOUT0_DIVIDE_G	positive := 2

Ports
rxP	in	slv ( NUM_LANE_G- 1 downto 0 )
rxN	in	slv ( NUM_LANE_G- 1 downto 0 )
pllClk	out	sl
refClk	in	sl
refRst	in	sl
deserClk	out	sl
deserRst	out	sl
deserData	out	Slv8Array ( NUM_LANE_G- 1 downto 0 )
dlyLoad	in	slv ( NUM_LANE_G- 1 downto 0 )
dlyCfg	in	Slv9Array ( NUM_LANE_G- 1 downto 0 )
axilClk	in	sl := ' 0 '
axilRst	in	sl := ' 0 '
axilReadMaster	in	AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C
axilReadSlave	out	AxiLiteReadSlaveType
axilWriteMaster	in	AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C
axilWriteSlave	out	AxiLiteWriteSlaveType

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The documentation for this design unit was generated from the following file:

• xilinx/7Series/general/rtl/SelectioDeser7Series.vhd