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SelectioDeserLane7Series Entity Reference
Inheritance diagram for SelectioDeserLane7Series:Entities | |
| SelectioDeserLane7Series.mapping | architecture |
Libraries | |
| ieee | |
| surf | |
| unisim | |
Use Clauses | |
| std_logic_1164 | |
| std_logic_arith | |
| std_logic_unsigned | |
| StdRtlPkg | Package <StdRtlPkg> |
| vcomponents | |
Generics | |
| TPD_G | time := 1 ns |
| IODELAY_GROUP_G | string := " DESER_GROUP " |
| REF_FREQ_G | real := 300 . 0 |
Ports | ||
| rxP | in | sl |
| rxN | in | sl |
| clkx4 | in | sl |
| clkx1 | in | sl |
| rstx1 | in | sl |
| dlyLoad | in | sl |
| dlyCfg | in | slv ( 8 downto 0 ) |
| dataOut | out | slv ( 7 downto 0 ) |
The documentation for this design unit was generated from the following file:
- xilinx/7Series/general/rtl/SelectioDeserLane7Series.vhd
