Sc18Is602Core Entity Reference

Inheritance diagram for Sc18Is602Core:

Collaboration diagram for Sc18Is602Core:

Entities
Sc18Is602Core.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_unsigned
std_logic_arith
StdRtlPkg	Package <StdRtlPkg>
AxiLitePkg	Package <AxiLitePkg>
I2cPkg	Package <I2cPkg>

Generics
TPD_G	time := 1 ns
I2C_BASE_ADDR_G	slv ( 2 downto 0 ) := " 000 "
I2C_SCL_FREQ_G	real := 100 . 0E + 3
I2C_MIN_PULSE_G	real := 100 . 0E - 9
SDO_MUX_SEL_MAP_G	Slv2Array ( 3 downto 0 ) := ( 0 = > " 00 " , 1 = > " 01 " , 2 = > " 10 " , 3 = > " 11 " )
ADDRESS_SIZE_G	IntegerArray ( 3 downto 0 ) := ( others = > 7 )
DATA_SIZE_G	IntegerArray ( 3 downto 0 ) := ( others = > 16 )
AXIL_CLK_FREQ_G	real := 156 . 25E + 6

Ports
i2ci	in	i2c_in_type
i2co	out	i2c_out_type
sdoMuxSel	out	slv ( 1 downto 0 )
axilReadMaster	in	AxiLiteReadMasterType
axilReadSlave	out	AxiLiteReadSlaveType
axilWriteMaster	in	AxiLiteWriteMasterType
axilWriteSlave	out	AxiLiteWriteSlaveType
axilClk	in	sl
axilRst	in	sl

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The documentation for this design unit was generated from the following file:

• devices/Nxp/Sc18Is602/rtl/Sc18Is602Core.vhd