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ADDRESS_MAX_SIZE_C | integer := maximum ( ADDRESS_SIZE_G ) |
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ADDR_SIZE_C | Slv2Array ( 3 downto 0 ) := ( 0 = > toSlv ( wordCount ( ADDRESS_SIZE_G ( 0 ) + 1 , 8 ) - 1 , 2 ) , 1 = > toSlv ( wordCount ( ADDRESS_SIZE_G ( 1 ) + 1 , 8 ) - 1 , 2 ) , 2 = > toSlv ( wordCount ( ADDRESS_SIZE_G ( 2 ) + 1 , 8 ) - 1 , 2 ) , 3 = > toSlv ( wordCount ( ADDRESS_SIZE_G ( 3 ) + 1 , 8 ) - 1 , 2 ) ) |
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DATA_SIZE_C | Slv2Array ( 3 downto 0 ) := ( 0 = > toSlv ( wordCount ( DATA_SIZE_G ( 0 ) , 8 ) - 1 , 2 ) , 1 = > toSlv ( wordCount ( DATA_SIZE_G ( 1 ) , 8 ) - 1 , 2 ) , 2 = > toSlv ( wordCount ( DATA_SIZE_G ( 2 ) , 8 ) - 1 , 2 ) , 3 = > toSlv ( wordCount ( DATA_SIZE_G ( 3 ) , 8 ) - 1 , 2 ) ) |
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READ_SIZE_C | Slv2Array ( 3 downto 0 ) := ( 0 = > toSlv ( wordCount ( ADDRESS_SIZE_G ( 0 ) + 1 + DATA_SIZE_G ( 0 ) , 8 ) - 1 , 2 ) , 1 = > toSlv ( wordCount ( ADDRESS_SIZE_G ( 1 ) + 1 + DATA_SIZE_G ( 1 ) , 8 ) - 1 , 2 ) , 2 = > toSlv ( wordCount ( ADDRESS_SIZE_G ( 2 ) + 1 + DATA_SIZE_G ( 2 ) , 8 ) - 1 , 2 ) , 3 = > toSlv ( wordCount ( ADDRESS_SIZE_G ( 3 ) + 1 + DATA_SIZE_G ( 3 ) , 8 ) - 1 , 2 ) ) |
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I2C_SCL_5xFREQ_C | real := 5 . 0 * I2C_SCL_FREQ_G |
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PRESCALE_C | natural := ( getTimeRatio ( AXIL_CLK_FREQ_G , I2C_SCL_5xFREQ_C ) ) - 1 |
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FILTER_C | natural := natural ( AXIL_CLK_FREQ_G* I2C_MIN_PULSE_G ) + 1 |
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I2C_ADDR_C | slv ( 9 downto 0 ) := ( " 000 " & " 0101 " & I2C_BASE_ADDR_G ) |
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MY_I2C_REG_MASTER_IN_INIT_C | I2cRegMasterInType := ( i2cAddr = > I2C_ADDR_C , tenbit = > ' 0 ' , regAddr = > ( others = > ' 0 ' ) , regWrData = > ( others = > ' 0 ' ) , regOp = > ' 0 ' , regAddrSkip = > ' 0 ' , regAddrSize = > " 00 " , regDataSize = > " 00 " , regReq = > ' 0 ' , busReq = > ' 0 ' , endianness = > ' 1 ' , repeatStart = > ' 0 ' , wrDataOnRd = > ' 0 ' ) |
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REG_INIT_C | RegType := ( sdoMuxSel = > " 00 " , axilReadSlave = > AXI_LITE_READ_SLAVE_INIT_C , axilWriteSlave = > AXI_LITE_WRITE_SLAVE_INIT_C , regIn = > MY_I2C_REG_MASTER_IN_INIT_C , state = > IDLE_S ) |
1.9.8