SaciPrepRdout Entity Reference

Entities
SaciPrepRdout.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_arith
std_logic_unsigned
StdRtlPkg	Package <StdRtlPkg>
AxiLitePkg	Package <AxiLitePkg>

Generics
TPD_G	time := 1 ns
MASK_REG_ADDR_G	slv ( 31 downto 0 ) := x " 00000034 "
MASK_REG_READ_G	boolean := true
SACI_BASE_ADDR_G	slv ( 31 downto 0 ) := x " 02000000 "
SACI_NUM_CHIPS_G	natural range 1 to 4 := 4

Ports
axilClk	in	sl
axilRst	in	sl
prepRdoutReq	in	sl
prepRdoutAck	out	sl
sAxilWriteMaster	in	AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C
sAxilWriteSlave	out	AxiLiteWriteSlaveType
sAxilReadMaster	in	AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C
sAxilReadSlave	out	AxiLiteReadSlaveType
mAxilWriteMaster	out	AxiLiteWriteMasterType
mAxilWriteSlave	in	AxiLiteWriteSlaveType
mAxilReadMaster	out	AxiLiteReadMasterType
mAxilReadSlave	in	AxiLiteReadSlaveType
asicMask	in	slv ( SACI_NUM_CHIPS_G- 1 downto 0 ) := ( others = > ' 0 ' )

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The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/SaciPrepRdout.vhd
• protocols/saci/saci1/rtl/SaciPrepRdout.vhd