SaciPrepRdout.rtl Architecture Reference

Architecture >> SaciPrepRdout::rtl

Functions
slv	asicBaseAddr ( asic: in natural )
slv	asicBaseAddr ( asic: in natural )

Processes
comb	( asicMask , axilRst , mAxilReadSlave , mAxilWriteSlave , prepRdoutReq , r , sAxilReadMaster , sAxilWriteMaster )
seq	( axilClk )
comb	( asicMask , axilRst , mAxilReadSlave , mAxilWriteSlave , prepRdoutReq , r , sAxilReadMaster , sAxilWriteMaster )
seq	( axilClk )

Constants

REG_INIT_C

RegType := ( asicMask = > ( others = > ' 0 ' ) , state = > S_IDLE_C , timer = > ( others = > ' 1 ' ) , asicCnt = > 0 , rdTimeout = > ( others = > ' 0 ' ) , rdFail = > ( others = > ' 0 ' ) , wrTimeout = > ( others = > ' 0 ' ) , wrFail = > ( others = > ' 0 ' ) , prepRdoutAck = > ' 0 ' , mAxilWriteMaster = > AXI_LITE_WRITE_MASTER_INIT_C , mAxilReadMaster = > AXI_LITE_READ_MASTER_INIT_C , sAxilWriteSlave = > AXI_LITE_WRITE_SLAVE_INIT_C , sAxilReadSlave = > AXI_LITE_READ_SLAVE_INIT_C )

Types
StateType	( S_IDLE_C , S_IS_ASIC_C , S_WRITE_C , S_WRITE_AXI_C , S_READ_C , S_READ_AXI_C )

Signals
r	RegType := REG_INIT_C
rin	RegType

Records
RegType

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The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/SaciPrepRdout.vhd
• protocols/saci/saci1/rtl/SaciPrepRdout.vhd