SaciAxiLiteMaster.rtl Architecture Reference

Architecture >> SaciAxiLiteMaster::rtl

Signals
axilReq	AxiLiteReqType
axilAck	AxiLiteAckType
rstOutL	sl
rstInL	sl
exec	sl
ack	sl
readL	sl
cmd	slv ( 6 downto 0 )
addr	slv ( 11 downto 0 )
wrData	slv ( 31 downto 0 )
rdData	slv ( 31 downto 0 )

Instantiations
u_sacislave_1	SaciSlave <Entity SaciSlave>
u_synchronizer_1	Synchronizer <Entity Synchronizer>
u_synchronizer_2	Synchronizer <Entity Synchronizer>
u_axilitemaster_1	AxiLiteMaster <Entity AxiLiteMaster>
u_sacislave_1	SaciSlave <Entity SaciSlave>
u_synchronizer_1	Synchronizer <Entity Synchronizer>
u_synchronizer_2	Synchronizer <Entity Synchronizer>
u_axilitemaster_1	AxiLiteMaster <Entity AxiLiteMaster>

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The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/SaciAxiLiteMaster.vhd
• protocols/saci/saci1/rtl/SaciAxiLiteMaster.vhd