RstSync.rtl Architecture Reference

Architecture >> RstSync::rtl

Processes
OUT_REG	( asyncRst , clk )
OUT_REG	( asyncRst , clk )

Signals
syncInt	sl := OUT_POLARITY_G

Instantiations
synchronizer_1	Synchronizer <Entity Synchronizer>
synchronizer_1	Synchronizer <Entity Synchronizer>

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The documentation for this design unit was generated from the following files:

• base/sync/rtl/RstSync.vhd
• build/SRC_VHDL/surf/RstSync.vhd