RoguePgp3Sim.sim Architecture Reference

Architecture >> RoguePgp3Sim::sim

Signals
clk	sl := ' 0 '
rst	sl := ' 1 '
txOut	Pgp3TxOutType := PGP3_TX_OUT_INIT_C
rxOut	Pgp3RxOutType := PGP3_RX_OUT_INIT_C

Instantiations
pwruprst_inst	PwrUpRst <Entity PwrUpRst>
u_pgp_vc	RogueTcpStreamWrap <Entity RogueTcpStreamWrap>
u_roguesidebandwrap_1	RogueSideBandWrap <Entity RogueSideBandWrap>
pwruprst_inst	PwrUpRst <Entity PwrUpRst>
u_pgp_vc	RogueTcpStreamWrap <Entity RogueTcpStreamWrap>
u_roguesidebandwrap_1	RogueSideBandWrap <Entity RogueSideBandWrap>

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The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/RoguePgp3Sim.vhd
• protocols/pgp/pgp3/core/tb/RoguePgp3Sim.vhd