RogueSideBandWrap Entity Reference

Inheritance diagram for RogueSideBandWrap:

Collaboration diagram for RogueSideBandWrap:

Entities
RogueSideBandWrap.RogueSideBandWrap	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_arith
std_logic_unsigned
StdRtlPkg	Package <StdRtlPkg>
AxiStreamPkg	Package <AxiStreamPkg>

Generics
TPD_G	time := 1 ns
PORT_NUM_G	natural range 1024 to 49151 := 9000

Ports
sysClk	in	sl
sysRst	in	sl
txOpCode	in	slv ( 7 downto 0 )
txOpCodeEn	in	sl
txRemData	in	slv ( 7 downto 0 )
rxOpCode	out	slv ( 7 downto 0 )
rxOpCodeEn	out	sl
rxRemData	out	slv ( 7 downto 0 )

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The documentation for this design unit was generated from the following files:

• axi/simlink/sim/RogueSideBandWrap.vhd
• build/SRC_VHDL/surf/RogueSideBandWrap.vhd