RoguePgp3Sim Entity Reference

Inheritance diagram for RoguePgp3Sim:

Collaboration diagram for RoguePgp3Sim:

Entities
RoguePgp3Sim.sim	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_arith
std_logic_unsigned
StdRtlPkg	Package <StdRtlPkg>
AxiLitePkg	Package <AxiLitePkg>
AxiStreamPkg	Package <AxiStreamPkg>
Pgp3Pkg	Package <Pgp3Pkg>

Generics
TPD_G	time := 1 ns
PORT_NUM_G	natural range 1024 to 49151 := 9000
NUM_VC_G	integer range 1 to 16 := 4
EN_SIDEBAND_G	boolean := true

Ports
pgpRefClk	in	sl
pgpGtRxP	in	sl
pgpGtRxN	in	sl
pgpGtTxP	out	sl := ' 0 '
pgpGtTxN	out	sl := ' 1 '
pgpClk	out	sl
pgpClkRst	out	sl
pgpRxIn	in	Pgp3RxInType
pgpRxOut	out	Pgp3RxOutType
pgpTxIn	in	Pgp3TxInType
pgpTxOut	out	Pgp3TxOutType
pgpTxMasters	in	AxiStreamMasterArray ( NUM_VC_G- 1 downto 0 )
pgpTxSlaves	out	AxiStreamSlaveArray ( NUM_VC_G- 1 downto 0 )
pgpRxMasters	out	AxiStreamMasterArray ( NUM_VC_G- 1 downto 0 )
pgpRxSlaves	in	AxiStreamSlaveArray ( NUM_VC_G- 1 downto 0 )
axilClk	in	sl := ' 0 '
axilRst	in	sl := ' 0 '
axilReadMaster	in	AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C
axilReadSlave	out	AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_EMPTY_OK_C
axilWriteMaster	in	AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C
axilWriteSlave	out	AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_EMPTY_OK_C

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The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/RoguePgp3Sim.vhd
• protocols/pgp/pgp3/core/tb/RoguePgp3Sim.vhd