RogueHtspSim.sim Architecture Reference

Architecture >> RogueHtspSim::sim

Signals
clk	sl := ' 0 '
rst	sl := ' 1 '
txOut	HtspTxOutType := HTSP_TX_OUT_INIT_C
rxOut	HtspRxOutType := HTSP_RX_OUT_INIT_C

Instantiations
pwruprst_inst	PwrUpRst <Entity PwrUpRst>
u_htsp_vc	RogueTcpStreamWrap <Entity RogueTcpStreamWrap>
u_roguesidebandwrap_1	RogueSideBandWrap <Entity RogueSideBandWrap>
pwruprst_inst	PwrUpRst <Entity PwrUpRst>
u_htsp_vc	RogueTcpStreamWrap <Entity RogueTcpStreamWrap>
u_roguesidebandwrap_1	RogueSideBandWrap <Entity RogueSideBandWrap>

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The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/RogueHtspSim.vhd
• protocols/htsp/core/tb/RogueHtspSim.vhd