RoCEv2AxisBucket.rtl Architecture Reference

Architecture >> RoCEv2AxisBucket::rtl

Processes
comb	( axisRst , byte_per_clk , packet_size , pipeAxisSlave , r , sAxisMaster )
seq	( axisClk , axisRst )

Constants
REG_INIT_C	RegType := ( state = > IDLE_S , armed = > ' 0 ' , count = > ( others = > ' 0 ' ) , go_idle = > false , axisSlave = > AXI_STREAM_SLAVE_INIT_C , axisMaster = > axiStreamMasterInit ( AXIS_CONFIG_G ) , rd_en = > ' 0 ' )
BUCKET_FRAC_C	slv ( FRAC_BITS_G- 1 downto 0 ) := ( others = > ' 0 ' )
BUCKET_SIZE_FULL_C	slv ( 31 + FRAC_BITS_G downto 0 ) := BUCKET_SIZE_G& BUCKET_FRAC_C

Types
FrameState	( IDLE_S , READ_S )

Signals
r	RegType := REG_INIT_C
rin	RegType
pipeAxisMaster	AxiStreamMasterType
pipeAxisSlave	AxiStreamSlaveType

Records
RegType

Instantiations
axistreampipeline_1	AxiStreamPipeline <Entity AxiStreamPipeline>

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The documentation for this design unit was generated from the following file:

• ethernet/RoCEv2/rtl/RoCEv2AxisBucket.vhd