SURF
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RoCEv2AxisBucket Entity Reference
+ Inheritance diagram for RoCEv2AxisBucket:
+ Collaboration diagram for RoCEv2AxisBucket:

Entities

RoCEv2AxisBucket.rtl  architecture
 

Libraries

ieee 
surf 

Use Clauses

std_logic_1164 
std_logic_arith 
std_logic_unsigned 
StdRtlPkg  Package <StdRtlPkg>
AxiStreamPkg  Package <AxiStreamPkg>
SsiPkg  Package <SsiPkg>

Generics

TPD_G  time := 1 ns
RST_ASYNC_G  boolean := false
PIPE_STAGES_G  natural := 0
RST_POLARITY_G  sl := ' 1 '
FRAC_BITS_G  natural := 16
BUCKET_SIZE_G  slv ( 31 downto 0 ) := x " 10000000 "
AXIS_CONFIG_G  AxiStreamConfigType

Ports

axisClk   in   sl
axisRst   in   sl
byte_per_clk   in   slv ( 15 + FRAC_BITS_G downto 0 )
packet_size   in   slv ( 31 downto 0 )
rd_en   out   sl
sAxisMaster   in   AxiStreamMasterType
sAxisSlave   out   AxiStreamSlaveType
mAxisMaster   out   AxiStreamMasterType
mAxisSlave   in   AxiStreamSlaveType

The documentation for this design unit was generated from the following file: