Architecture >> RoCEv2AxiStreamRdmaWrapper::rtl

Processes
sAxisComb	( S_AXIS_TVALID , S_AXIS_TDATA , S_AXIS_TKEEP , S_AXIS_TLAST )
obUdpComb	( S_OBUDP_TVALID , S_OBUDP_TDATA , S_OBUDP_TKEEP , S_OBUDP_TLAST )

Signals
axilClk	sl
axilRst	sl
axilReadMaster	AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C
axilReadSlave	AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_INIT_C
axilWriteMaster	AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C
axilWriteSlave	AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_INIT_C
sAxisMaster	AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C
sAxisSlave	AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C
obUdpMaster	AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C
obUdpSlave	AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C
ibUdpMaster	AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C
ibUdpSlave	AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C

Instantiations
u_shimlayer	SlaveAxiLiteIpIntegrator <Entity SlaveAxiLiteIpIntegrator>
u_dut	RoCEv2AxiStreamRdma <Entity RoCEv2AxiStreamRdma>

The documentation for this design unit was generated from the following file:

Processes

Signals