PgpGthCoreWrapper.mapping Architecture Reference

Architecture >> PgpGthCoreWrapper::mapping

Components
PgpGthCore

Signals
drpAddr	slv ( 9 downto 0 )
drpDi	slv ( 15 downto 0 )
drpDo	slv ( 15 downto 0 )
drpEn	sl
drpWe	sl
drpRdy	sl
dummy0_6	slv ( 5 downto 0 )
dummy1_14	slv ( 13 downto 0 )
dummy2_14	slv ( 13 downto 0 )
dummy3_6	slv ( 5 downto 0 )
dummy4_1	sl
dummy5_1	sl
txctrl2	slv ( 7 downto 0 )
drpAddr	slv ( 8 downto 0 )

Instantiations
u_pgpgthcore	pgpgthcore
u_axilitetodrp_1	AxiLiteToDrp <Entity AxiLiteToDrp>
u_pgpgthcore	pgpgthcore
u_axilitetodrp_1	AxiLiteToDrp <Entity AxiLiteToDrp>

---

The documentation for this design unit was generated from the following files:

• protocols/pgp/pgp2b/gthUltraScale+/rtl/PgpGthCoreWrapper.vhd
• protocols/pgp/pgp2b/gthUltraScale/rtl/PgpGthCoreWrapper.vhd