PgpGthCoreWrapper Entity Reference

Inheritance diagram for PgpGthCoreWrapper:

Collaboration diagram for PgpGthCoreWrapper:

Entities
PgpGthCoreWrapper.mapping	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
StdRtlPkg	Package <StdRtlPkg>
AxiLitePkg	Package <AxiLitePkg>

Generics
TPD_G	time := 1 ns

Ports
stableClk	in	sl
stableRst	in	sl
gtRefClk	in	sl
gtRxP	in	sl
gtRxN	in	sl
gtTxP	out	sl
gtTxN	out	sl
rxReset	in	sl
rxUsrClkActive	in	sl
rxResetDone	out	sl
rxUsrClk	in	sl
rxData	out	slv ( 15 downto 0 )
rxDataK	out	slv ( 1 downto 0 )
rxDispErr	out	slv ( 1 downto 0 )
rxDecErr	out	slv ( 1 downto 0 )
rxPolarity	in	sl
rxOutClk	out	sl
txReset	in	sl
txUsrClk	in	sl
txUsrClkActive	in	sl
txResetDone	out	sl
txData	in	slv ( 15 downto 0 )
txDataK	in	slv ( 1 downto 0 )
txPolarity	in	sl
txOutClk	out	sl
loopback	in	slv ( 2 downto 0 )
axilClk	in	sl := ' 0 '
axilRst	in	sl := ' 0 '
axilReadMaster	in	AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C
axilReadSlave	out	AxiLiteReadSlaveType
axilWriteMaster	in	AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C
axilWriteSlave	out	AxiLiteWriteSlaveType

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The documentation for this design unit was generated from the following files:

• protocols/pgp/pgp2b/gthUltraScale+/rtl/PgpGthCoreWrapper.vhd
• protocols/pgp/pgp2b/gthUltraScale/rtl/PgpGthCoreWrapper.vhd