Pgp4RxEb.rtl Architecture Reference

Architecture >> Pgp4RxEb::rtl

Processes
comb	( phyRxData , phyRxHeader , phyRxRst , phyRxValid , r )
seq	( phyRxClk , phyRxRst )
comb	( phyRxData , phyRxHeader , phyRxRst , phyRxValid , r )
seq	( phyRxClk , phyRxRst )

Constants
REG_INIT_C	RegType := ( linkError = > ' 0 ' , dataValid = > ' 0 ' , remLinkData = > ( others = > ' 0 ' ) , fifoIn = > ( others = > ' 0 ' ) , fifoWrEn = > ' 0 ' )

Signals
r	RegType := REG_INIT_C
rin	RegType
valid	sl
overflowInt	sl

Records
RegType

Instantiations
u_remlinkdata	SynchronizerFifo <Entity SynchronizerFifo>
u_fifoasync_1	FifoAsync <Entity FifoAsync>
u_overflow	SynchronizerOneShot <Entity SynchronizerOneShot>
u_linkerror	SynchronizerOneShot <Entity SynchronizerOneShot>
u_remlinkdata	SynchronizerFifo <Entity SynchronizerFifo>
u_fifoasync_1	FifoAsync <Entity FifoAsync>
u_overflow	SynchronizerOneShot <Entity SynchronizerOneShot>
u_linkerror	SynchronizerOneShot <Entity SynchronizerOneShot>

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The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/Pgp4RxEb.vhd
• protocols/pgp/pgp4/core/rtl/Pgp4RxEb.vhd