Pgp4LiteRxLowSpeedWrapper Entity Reference

Inheritance diagram for Pgp4LiteRxLowSpeedWrapper:

Collaboration diagram for Pgp4LiteRxLowSpeedWrapper:

Entities
Pgp4LiteRxLowSpeedWrapper.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
StdRtlPkg	Package <StdRtlPkg>
AxiLitePkg	Package <AxiLitePkg>
AxiStreamPkg	Package <AxiStreamPkg>
Pgp4Pkg	Package <Pgp4Pkg>

Ports
clk	in	sl
rst	in	sl
txValid	in	sl
txReady	out	sl
txData	in	slv ( 63 downto 0 )
txSof	in	sl
txEof	in	sl
txEofe	in	sl
dlyLoad	out	sl
dlyCfg	out	slv ( 8 downto 0 )
rxValid	out	sl
rxLast	out	sl
rxData	out	slv ( 63 downto 0 )
rxDest	out	slv ( 7 downto 0 )
rxUser	out	slv ( 15 downto 0 )
S_AXI_ACLK	in	std_logic := ' 0 '
S_AXI_ARESETN	in	std_logic := ' 0 '
S_AXI_AWADDR	in	std_logic_vector ( 11 downto 0 ) := ( others = > ' 0 ' )
S_AXI_AWPROT	in	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
S_AXI_AWVALID	in	std_logic := ' 0 '
S_AXI_AWREADY	out	std_logic
S_AXI_WDATA	in	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
S_AXI_WSTRB	in	std_logic_vector ( 3 downto 0 ) := ( others = > ' 1 ' )
S_AXI_WVALID	in	std_logic := ' 0 '
S_AXI_WREADY	out	std_logic
S_AXI_BRESP	out	std_logic_vector ( 1 downto 0 )
S_AXI_BVALID	out	std_logic
S_AXI_BREADY	in	std_logic := ' 0 '
S_AXI_ARADDR	in	std_logic_vector ( 11 downto 0 ) := ( others = > ' 0 ' )
S_AXI_ARPROT	in	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
S_AXI_ARVALID	in	std_logic := ' 0 '
S_AXI_ARREADY	out	std_logic
S_AXI_RDATA	out	std_logic_vector ( 31 downto 0 )
S_AXI_RRESP	out	std_logic_vector ( 1 downto 0 )
S_AXI_RVALID	out	std_logic
S_AXI_RREADY	in	std_logic := ' 0 '

---

The documentation for this design unit was generated from the following file:

• protocols/pgp/pgp4/core/wrappers/Pgp4LiteRxLowSpeedWrapper.vhd