Pgp4CoreLite.rtl Architecture Reference

Architecture >> Pgp4CoreLite::rtl

Signals
locRxLinkReady	sl := ' 0 '
remRxFifoCtrl	AxiStreamCtrlArray ( NUM_VC_G- 1 downto 0 ) := ( others = > AXI_STREAM_CTRL_UNUSED_C )
remRxLinkReady	sl := ' 0 '
pgpTxInInt	Pgp4TxInType := PGP4_TX_IN_INIT_C
pgpTxOutInt	Pgp4TxOutType := PGP4_TX_OUT_INIT_C
pgpRxInInt	Pgp4RxInType := PGP4_RX_IN_INIT_C
pgpRxOutInt	Pgp4RxOutType := PGP4_RX_OUT_INIT_C

Instantiations
u_pgp4tx_1	Pgp4TxLite <Entity Pgp4TxLite>
u_pgp4rx_1	Pgp4Rx <Entity Pgp4Rx>
u_pgp4axil	Pgp4AxiL <Entity Pgp4AxiL>
u_pgp4tx_1	Pgp4TxLite <Entity Pgp4TxLite>
u_pgp4rx_1	Pgp4Rx <Entity Pgp4Rx>
u_pgp4axil	Pgp4AxiL <Entity Pgp4AxiL>

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The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/Pgp4CoreLite.vhd
• protocols/pgp/pgp4/core/rtl/Pgp4CoreLite.vhd