Pgp3RxEb.rtl Architecture Reference

Architecture >> Pgp3RxEb::rtl

Processes
comb	( phyRxData , phyRxHeader , phyRxRst , phyRxValid , r )
seq	( phyRxClk )
comb	( phyRxData , phyRxHeader , phyRxRst , phyRxValid , r )
seq	( phyRxClk )

Constants
REG_INIT_C	RegType := ( remLinkData = > ( others = > ' 0 ' ) , fifoIn = > ( others = > ' 0 ' ) , fifoWrEn = > ' 0 ' )

Signals
r	RegType := REG_INIT_C
rin	RegType
valid	sl
overflowInt	sl

Records
RegType

Instantiations
u_remlinkdata	SynchronizerFifo <Entity SynchronizerFifo>
u_fifoasync_1	FifoAsync <Entity FifoAsync>
u_rstsync_1	RstSync <Entity RstSync>
u_remlinkdata	SynchronizerFifo <Entity SynchronizerFifo>
u_fifoasync_1	FifoAsync <Entity FifoAsync>
u_rstsync_1	RstSync <Entity RstSync>

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The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/Pgp3RxEb.vhd
• protocols/pgp/pgp3/core/rtl/Pgp3RxEb.vhd