Pgp3Gtx7Wrapper.rtl Architecture Reference

Architecture >> Pgp3Gtx7Wrapper::rtl

Constants
NUM_AXIL_MASTERS_C	integer := NUM_LANES_G+ 1
QPLL_AXIL_INDEX_C	integer := NUM_AXIL_MASTERS_C- 1
XBAR_CONFIG_C	AxiLiteCrossbarMasterConfigArray ( NUM_AXIL_MASTERS_C- 1 downto 0 ) := genAxiLiteConfig ( NUM_AXIL_MASTERS_C , AXIL_BASE_ADDR_G , 16 , 13 )

Signals
qpllLock	slv ( 3 downto 0 ) := ( others = > ' 0 ' )
qpllClk	slv ( 3 downto 0 ) := ( others = > ' 0 ' )
qpllRefclk	slv ( 3 downto 0 ) := ( others = > ' 0 ' )
qpllRefClkLost	slv ( 3 downto 0 ) := ( others = > ' 0 ' )
qpllRst	slv ( 3 downto 0 ) := ( others = > ' 0 ' )
gtTxOutClk	slv ( 3 downto 0 ) := ( others = > ' 0 ' )
gtTxPllRst	slv ( 3 downto 0 ) := ( others = > ' 0 ' )
gtTxPllLock	slv ( 3 downto 0 ) := ( others = > ' 0 ' )
txPllClk	slv ( 1 downto 0 ) := ( others = > ' 0 ' )
txPllRst	slv ( 1 downto 0 ) := ( others = > ' 0 ' )
lockedStrobe	slv ( 3 downto 0 ) := ( others = > ' 0 ' )
pllLock	sl
pgpRefClkDiv2	sl
pgpRefClk	sl
axilReadMasters	AxiLiteReadMasterArray ( NUM_AXIL_MASTERS_C- 1 downto 0 ) := ( others = > AXI_LITE_READ_MASTER_INIT_C )
axilReadSlaves	AxiLiteReadSlaveArray ( NUM_AXIL_MASTERS_C- 1 downto 0 ) := ( others = > AXI_LITE_READ_SLAVE_EMPTY_DECERR_C )
axilWriteMasters	AxiLiteWriteMasterArray ( NUM_AXIL_MASTERS_C- 1 downto 0 ) := ( others = > AXI_LITE_WRITE_MASTER_INIT_C )
axilWriteSlaves	AxiLiteWriteSlaveArray ( NUM_AXIL_MASTERS_C- 1 downto 0 ) := ( others = > AXI_LITE_WRITE_SLAVE_EMPTY_DECERR_C )

Instantiations
u_bufg	bufg
u_pgprefclk	ibufds_gte2
u_xbar	AxiLiteCrossbar <Entity AxiLiteCrossbar>
u_qpll	Pgp3Gtx7Qpll <Entity Pgp3Gtx7Qpll>
u_pgp	Pgp3Gtx7 <Entity Pgp3Gtx7>
u_pwruprst	PwrUpRst <Entity PwrUpRst>
u_tx_pll	ClockManager7 <Entity ClockManager7>
u_rogue	RoguePgp3Sim <Entity RoguePgp3Sim>

---

The documentation for this design unit was generated from the following file:

• protocols/pgp/pgp3/gtx7/rtl/Pgp3Gtx7Wrapper.vhd