Architecture >> Pgp3GthUs::rtl

Constants
NUM_AXIL_MASTERS_C	integer := 2
PGP_AXIL_INDEX_C	integer := 0
DRP_AXIL_INDEX_C	integer := 1
XBAR_CONFIG_C	AxiLiteCrossbarMasterConfigArray ( NUM_AXIL_MASTERS_C- 1 downto 0 ) := ( PGP_AXIL_INDEX_C = > ( baseAddr = > AXIL_BASE_ADDR_G , addrBits = > 12 , connectivity = > X " FFFF " ) , DRP_AXIL_INDEX_C = > ( baseAddr = > AXIL_BASE_ADDR_G+ X " 1000 " , addrBits = > 12 , connectivity = > X " FFFF " ) )
XBAR_CONFIG_C	AxiLiteCrossbarMasterConfigArray ( NUM_AXIL_MASTERS_C- 1 downto 0 ) := ( PGP_AXIL_INDEX_C = > ( baseAddr = > AXIL_BASE_ADDR_G , addrBits = > 12 , connectivity = > X " FFFF " ) , DRP_AXIL_INDEX_C = > ( baseAddr = > AXIL_BASE_ADDR_G+ X " 1000 " , addrBits = > 11 , connectivity = > X " FFFF " ) )

Signals
pgpRxClkInt	sl
pgpRxRstInt	sl
pgpTxClkInt	sl
pgpTxRstInt	sl
phyRxClk	sl
phyRxRst	sl
phyRxInit	sl
phyRxActive	sl
phyRxValid	sl
phyRxHeader	slv ( 1 downto 0 )
phyRxData	slv ( 63 downto 0 )
phyRxStartSeq	sl
phyRxSlip	sl
phyTxActive	sl
phyTxStart	sl
phyTxData	slv ( 63 downto 0 )
phyTxHeader	slv ( 1 downto 0 )
axilReadMasters	AxiLiteReadMasterArray ( NUM_AXIL_MASTERS_C- 1 downto 0 ) := ( others = > AXI_LITE_READ_MASTER_INIT_C )
axilReadSlaves	AxiLiteReadSlaveArray ( NUM_AXIL_MASTERS_C- 1 downto 0 ) := ( others = > AXI_LITE_READ_SLAVE_EMPTY_DECERR_C )
axilWriteMasters	AxiLiteWriteMasterArray ( NUM_AXIL_MASTERS_C- 1 downto 0 ) := ( others = > AXI_LITE_WRITE_MASTER_INIT_C )
axilWriteSlaves	AxiLiteWriteSlaveArray ( NUM_AXIL_MASTERS_C- 1 downto 0 ) := ( others = > AXI_LITE_WRITE_SLAVE_EMPTY_DECERR_C )
loopback	slv ( 2 downto 0 )
txDiffCtrl	slv ( 4 downto 0 )
txPreCursor	slv ( 4 downto 0 )
txPostCursor	slv ( 4 downto 0 )
gtRxUserReset	sl
gtTxUserReset	sl

Instantiations
u_xbar	AxiLiteCrossbar <Entity AxiLiteCrossbar>
u_pgp3core_1	Pgp3Core <Entity Pgp3Core>
u_pgp3gthusipwrapper_1	Pgp3GthUsIpWrapper <Entity Pgp3GthUsIpWrapper>
u_xbar	AxiLiteCrossbar <Entity AxiLiteCrossbar>
u_pgp3core_1	Pgp3Core <Entity Pgp3Core>
u_pgp3gthusipwrapper_1	Pgp3GthUsIpWrapper <Entity Pgp3GthUsIpWrapper>

The documentation for this design unit was generated from the following files:

Constants

Signals