Pgp3GthUsIpWrapper.mapping Architecture Reference

Architecture >> Pgp3GthUsIpWrapper::mapping

Components
Pgp3GthUsIp15G
Pgp3GthUsIp12G
Pgp3GthUsIp10G
Pgp3GthUsIp6G
Pgp3GthUsIp3G

Signals
dummy1	sl
dummy2	sl
dummy3	slv ( 3 downto 0 )
dummy4	sl
dummy5	sl
dummy6	sl
dummy7	sl
dummy8	sl
dummy9	sl
dummy10	sl
dummy11	sl
zeroBit	sl
txsequence_in	slv ( 6 downto 0 )
txheader_in	slv ( 5 downto 0 )
rxUsrClk2Int	sl
rxUsrClkActiveInt	sl
txUsrClk2Int	sl
txUsrClkActiveInt	sl
drpAddr	slv ( 9 downto 0 ) := ( others = > ' 0 ' )
drpDi	slv ( 15 downto 0 ) := ( others = > ' 0 ' )
drpDo	slv ( 15 downto 0 ) := ( others = > ' 0 ' )
drpEn	sl := ' 0 '
drpWe	sl := ' 0 '
drpRdy	sl := ' 0 '
drpAddr	slv ( 8 downto 0 ) := ( others = > ' 0 ' )

Instantiations
u_rstsync_tx	RstSync <Entity RstSync>
u_rstsync_rx	RstSync <Entity RstSync>
u_pgp3gthusip	pgp3gthusip15g
u_pgp3gthusip	pgp3gthusip12g
u_pgp3gthusip	pgp3gthusip10g
u_pgp3gthusip	pgp3gthusip6g
u_pgp3gthusip	pgp3gthusip3g
u_axilitetodrp_1	AxiLiteToDrp <Entity AxiLiteToDrp>
u_rstsync_tx	RstSync <Entity RstSync>
u_rstsync_rx	RstSync <Entity RstSync>
u_pgp3gthusip	pgp3gthusip10g
u_pgp3gthusip	pgp3gthusip6g
u_pgp3gthusip	pgp3gthusip3g
u_axilitetodrp_1	AxiLiteToDrp <Entity AxiLiteToDrp>

---

The documentation for this design unit was generated from the following files:

• protocols/pgp/pgp3/gthUs+/rtl/Pgp3GthUsIpWrapper.vhd
• protocols/pgp/pgp3/gthUs/rtl/Pgp3GthUsIpWrapper.vhd