Pgp2bGtx7MultiLane.rtl Architecture Reference

Architecture >> Pgp2bGtx7MultiLane::rtl

Signals
gtQPllResets	slv ( ( LANE_CNT_G- 1 ) downto 0 )
cPllLock	slv ( ( LANE_CNT_G- 1 ) downto 0 )
pgpRxMmcmResets	slv ( ( LANE_CNT_G- 1 ) downto 0 )
pgpRxRecClock	slv ( ( LANE_CNT_G- 1 ) downto 0 )
gtRxResetDone	slv ( ( LANE_CNT_G- 1 ) downto 0 )
gtRxUserReset	sl
gtRxUserResetIn	sl
phyRxLanesIn	Pgp2bRxPhyLaneInArray ( ( LANE_CNT_G- 1 ) downto 0 )
phyRxLanesOut	Pgp2bRxPhyLaneOutArray ( ( LANE_CNT_G- 1 ) downto 0 )
phyRxReady	sl
phyRxInit	sl
rxChBondLevel	slv ( 2 downto 0 )
rxChBondIn	Slv5Array ( LANE_CNT_G- 1 downto 0 )
rxChBondOut	Slv5Array ( LANE_CNT_G- 1 downto 0 )
pgpTxMmcmResets	slv ( ( LANE_CNT_G- 1 ) downto 0 )
pgpTxRecClock	slv ( ( LANE_CNT_G- 1 ) downto 0 )
gtTxResetDone	slv ( ( LANE_CNT_G- 1 ) downto 0 )
gtTxUserResetIn	sl
phyTxLanesOut	Pgp2bTxPhyLaneOutArray ( ( LANE_CNT_G- 1 ) downto 0 )
phyTxReady	sl
drpRdy	slv ( LANE_CNT_G- 1 downto 0 )
drpEn	slv ( LANE_CNT_G- 1 downto 0 )
drpWe	slv ( LANE_CNT_G- 1 downto 0 )
drpAddr	Slv9Array ( LANE_CNT_G- 1 downto 0 )
drpDi	Slv16Array ( LANE_CNT_G- 1 downto 0 )
drpDo	Slv16Array ( LANE_CNT_G- 1 downto 0 )

Instantiations
u_pgp2blane	Pgp2bLane <Entity Pgp2bLane>
gtx7core_inst	Gtx7Core <Entity Gtx7Core>
u_axilitetodrp	AxiLiteToDrp <Entity AxiLiteToDrp>

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The documentation for this design unit was generated from the following file:

• protocols/pgp/pgp2b/gtx7/rtl/Pgp2bGtx7MultiLane.vhd