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Pgp2bGtx7FixedLatWrapperTb.tb Architecture Reference
Architecture >> Pgp2bGtx7FixedLatWrapperTb::tb

Constants

TPD_G  time := 1 ns
SIM_GTRESET_SPEEDUP_G  string := " TRUE "
SIM_VERSION_G  string := " 4.0 "
SIMULATION_G  boolean := true
VC_INTERLEAVE_G  integer := 0
PAYLOAD_CNT_TOP_G  integer := 7
NUM_VC_EN_G  integer range 1 to 4 := 4
TX_ENABLE_G  boolean := true
RX_ENABLE_G  boolean := true
TX_CM_EN_G  boolean := false
TX_CM_TYPE_G  string := " MMCM "
TX_CM_CLKIN_PERIOD_G  real := 8 . 000
TX_CM_DIVCLK_DIVIDE_G  natural := 8
TX_CM_CLKFBOUT_MULT_F_G  real := 8 . 000
TX_CM_CLKOUT_DIVIDE_F_G  real := 8 . 000
RX_CM_EN_G  boolean := false
RX_CM_TYPE_G  string := " MMCM "
RX_CM_CLKIN_PERIOD_G  real := 8 . 000
RX_CM_DIVCLK_DIVIDE_G  natural := 8
RX_CM_CLKFBOUT_MULT_F_G  real := 8 . 000
RX_CM_CLKOUT_DIVIDE_F_G  real := 8 . 000
RX_OS_CFG_G  bit_vector := " 0000010000000 "
RXCDR_CFG_G  bit_vector := x " 03000023FF40200020 "
RXDFEXYDEN_G  sl := ' 0 '
RX_DFE_KL_CFG2_G  bit_vector := x " 3008E56A "
STABLE_CLK_SRC_G  string := " gtClk0 "
TX_REFCLK_SRC_G  string := " gtClk0 "
RX_REFCLK_SRC_G  string := " gtClk1 "
CPLL_CFG_G  Gtx7CPllCfgType := getGtx7CPllCfg ( 250 . 0E + 6 , 3 . 125E + 9 )
QPLL_CFG_G  Gtx7QPllCfgType := getGtx7QPllCfg ( 156 . 25E + 6 , 3 . 125E + 9 )
TX_PLL_G  string := " QPLL "
RX_PLL_G  string := " CPLL "

Signals

stableClkIn  sl := ' 0 '
extRst  sl
txPllLock  sl
rxPllLock  sl
pgpTxClkOut  sl
pgpRxClkOut  sl
pgpRxRstOut  sl
stableClkOut  sl
pgpRxIn  Pgp2bRxInType := PGP2B_RX_IN_INIT_C
pgpRxOut  Pgp2bRxOutType
pgpTxIn  Pgp2bTxInType := PGP2B_TX_IN_INIT_C
pgpTxOut  Pgp2bTxOutType
pgpTxMasters  AxiStreamMasterArray ( 3 downto 0 ) := ( others = > AXI_STREAM_MASTER_INIT_C )
pgpTxSlaves  AxiStreamSlaveArray ( 3 downto 0 )
pgpRxMasters  AxiStreamMasterArray ( 3 downto 0 )
pgpRxMasterMuxed  AxiStreamMasterType
pgpRxCtrl  AxiStreamCtrlArray ( 3 downto 0 ) := ( others = > AXI_STREAM_CTRL_UNUSED_C )
gtgClk  sl := ' 0 '
gtClk0P  sl := ' 0 '
gtClk0N  sl := ' 0 '
gtClk1P  sl := ' 0 '
gtClk1N  sl := ' 0 '
gtTxP  sl
gtTxN  sl
gtRxP  sl
gtRxN  sl
txPreCursor  slv ( 4 downto 0 ) := ( others = > ' 0 ' )
txPostCursor  slv ( 4 downto 0 ) := ( others = > ' 0 ' )
txDiffCtrl  slv ( 3 downto 0 ) := " 1000 "
axilClk  sl := ' 0 '
axilRst  sl := ' 0 '
axilReadMaster  AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C
axilReadSlave  AxiLiteReadSlaveType
axilWriteMaster  AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C
axilWriteSlave  AxiLiteWriteSlaveType

Instantiations

u_pgp2bgtx7fixedlatwrapper  Pgp2bGtx7FixedLatWrapper <Entity Pgp2bGtx7FixedLatWrapper>
u_clkrst_gt_clk0  ClkRst <Entity ClkRst>
u_clkrst_gt_clk1  ClkRst <Entity ClkRst>

The documentation for this design unit was generated from the following file: