Pgp2bGtx7FixedLatWrapper Entity Reference

Inheritance diagram for Pgp2bGtx7FixedLatWrapper:

Collaboration diagram for Pgp2bGtx7FixedLatWrapper:

Entities
Pgp2bGtx7FixedLatWrapper.rtl	architecture

Libraries
ieee
surf
unisim

Use Clauses
std_logic_1164
numeric_std
StdRtlPkg	Package <StdRtlPkg>
AxiStreamPkg	Package <AxiStreamPkg>
Pgp2bPkg	Package <Pgp2bPkg>
AxiLitePkg	Package <AxiLitePkg>
Gtx7CfgPkg	Package <Gtx7CfgPkg>
vcomponents

Generics
TPD_G	time := 1 ns
COMMON_CLK_G	boolean := false
SIM_GTRESET_SPEEDUP_G	string := " FALSE "
SIM_VERSION_G	string := " 4.0 "
SIMULATION_G	boolean := false
VC_INTERLEAVE_G	integer := 0
PAYLOAD_CNT_TOP_G	integer := 7
NUM_VC_EN_G	integer range 1 to 4 := 4
EXT_RST_POLARITY_G	sl := ' 1 '
TX_POLARITY_G	sl := ' 0 '
RX_POLARITY_G	sl := ' 0 '
TX_ENABLE_G	boolean := true
RX_ENABLE_G	boolean := true
TX_CM_EN_G	boolean := false
TX_CM_TYPE_G	string := " MMCM "
TX_CM_BANDWIDTH_G	string := " OPTIMIZED "
TX_CM_CLKIN_PERIOD_G	real := 8 . 000
TX_CM_DIVCLK_DIVIDE_G	natural := 8
TX_CM_CLKFBOUT_MULT_F_G	real := 8 . 000
TX_CM_CLKFBOUT_MULT_G	integer range 2 to 64 := 8
TX_CM_CLKOUT_DIVIDE_F_G	real := 8 . 000
TX_CM_CLKOUT_DIVIDE_G	integer range 1 to 128 := 8
RX_CM_EN_G	boolean := false
RX_CM_TYPE_G	string := " MMCM "
RX_CM_BANDWIDTH_G	string := " OPTIMIZED "
RX_CM_CLKIN_PERIOD_G	real := 8 . 000
RX_CM_DIVCLK_DIVIDE_G	natural := 8
RX_CM_CLKFBOUT_MULT_F_G	real := 8 . 000
RX_CM_CLKFBOUT_MULT_G	integer range 2 to 64 := 8
RX_CM_CLKOUT_DIVIDE_F_G	real := 8 . 000
RX_CM_CLKOUT_DIVIDE_G	integer range 1 to 128 := 8
PMA_RSV_G	bit_vector := x " 00018480 "
RX_OS_CFG_G	bit_vector := " 0000010000000 "
RXCDR_CFG_G	bit_vector := x " 03000023FF40200020 "
RXDFEXYDEN_G	sl := ' 0 '
RX_DFE_KL_CFG2_G	bit_vector := x " 3008E56A "
STABLE_CLK_SRC_G	string := " stableClkIn "
TX_REFCLK_SRC_G	string := " gtClk0 "
TX_USER_CLK_SRC_G	string := " txRefClk "
TX_BUF_EN_G	boolean := false
TX_OUTCLK_SRC_G	string := " PLLREFCLK "
TX_PHASE_ALIGN_G	string := " MANUAL "
RX_REFCLK_SRC_G	string := " gtClk1 "
CPLL_CFG_G	Gtx7CPllCfgType := getGtx7CPllCfg ( 250 . 0E + 6 , 3 . 125E + 9 )
QPLL_CFG_G	Gtx7QPllCfgType := getGtx7QPllCfg ( 156 . 25E + 6 , 3 . 125E + 9 )
TX_PLL_G	string := " QPLL "
RX_PLL_G	string := " CPLL "

Ports
stableClkIn	in	sl := ' 0 '
extRst	in	sl := ' 0 '
txPllLock	out	sl
rxPllLock	out	sl
pgpTxClkOut	out	sl
pgpTxRstOut	out	sl
pgpRxClkOut	out	sl
pgpRxRstOut	out	sl
stableClkOut	out	sl
pgpRxIn	in	Pgp2bRxInType
pgpRxOut	out	Pgp2bRxOutType
pgpTxIn	in	Pgp2bTxInType
pgpTxOut	out	Pgp2bTxOutType
pgpTxMasters	in	AxiStreamMasterArray ( 3 downto 0 ) := ( others = > AXI_STREAM_MASTER_INIT_C )
pgpTxSlaves	out	AxiStreamSlaveArray ( 3 downto 0 )
pgpRxMasters	out	AxiStreamMasterArray ( 3 downto 0 )
pgpRxMasterMuxed	out	AxiStreamMasterType
pgpRxCtrl	in	AxiStreamCtrlArray ( 3 downto 0 ) := ( others = > AXI_STREAM_CTRL_UNUSED_C )
gtgClk	in	sl := ' 0 '
gtClk0P	in	sl := ' 0 '
gtClk0N	in	sl := ' 0 '
gtClk1P	in	sl := ' 0 '
gtClk1N	in	sl := ' 0 '
gtTxP	out	sl
gtTxN	out	sl
gtRxP	in	sl
gtRxN	in	sl
txPreCursor	in	slv ( 4 downto 0 ) := ( others = > ' 0 ' )
txPostCursor	in	slv ( 4 downto 0 ) := ( others = > ' 0 ' )
txDiffCtrl	in	slv ( 3 downto 0 ) := " 1000 "
axilClk	in	sl := ' 0 '
axilRst	in	sl := ' 0 '
axilReadMaster	in	AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C
axilReadSlave	out	AxiLiteReadSlaveType
axilWriteMaster	in	AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C
axilWriteSlave	out	AxiLiteWriteSlaveType

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The documentation for this design unit was generated from the following file:

• protocols/pgp/pgp2b/gtx7/rtl/Pgp2bGtx7FixedLatWrapper.vhd