Pgp2bGtp7VarLatWrapper Entity Reference

Inheritance diagram for Pgp2bGtp7VarLatWrapper:

Collaboration diagram for Pgp2bGtp7VarLatWrapper:

Entities
Pgp2bGtp7VarLatWrapper.mapping	architecture

Libraries
ieee
surf
unisim

Use Clauses
std_logic_1164
StdRtlPkg	Package <StdRtlPkg>
AxiStreamPkg	Package <AxiStreamPkg>
Pgp2bPkg	Package <Pgp2bPkg>
AxiLitePkg	Package <AxiLitePkg>
vcomponents

Generics
TPD_G	time := 1 ns
COMMON_CLK_G	boolean := false
SIMULATION_G	boolean := false
DYNAMIC_QPLL_G	boolean := false
CLKIN_PERIOD_G	real := 6 . 4
DIVCLK_DIVIDE_G	natural range 1 to 106 := 1
CLKFBOUT_MULT_F_G	real range 1 . 0 to 64 . 0 := 6 . 0
CLKOUT0_DIVIDE_F_G	real range 1 . 0 to 128 . 0 := 6 . 0
QPLL_REFCLK_SEL_G	bit_vector := " 001 "
QPLL_FBDIV_IN_G	natural range 1 to 5 := 5
QPLL_FBDIV_45_IN_G	natural range 4 to 5 := 5
QPLL_REFCLK_DIV_IN_G	natural range 1 to 2 := 1
RXOUT_DIV_G	natural := 2
TXOUT_DIV_G	natural := 2
RX_CLK25_DIV_G	natural := 5
TX_CLK25_DIV_G	natural := 5
RX_OS_CFG_G	bit_vector := " 0000010000000 "
RXCDR_CFG_G	bit_vector := x " 0001107FE206021081010 "
RXLPM_INCM_CFG_G	bit := ' 0 '
RXLPM_IPCM_CFG_G	bit := ' 1 '
TX_POLARITY_G	sl := ' 0 '
RX_POLARITY_G	sl := ' 0 '
TX_ENABLE_G	boolean := true
RX_ENABLE_G	boolean := true
PAYLOAD_CNT_TOP_G	integer := 7
VC_INTERLEAVE_G	integer := 1
NUM_VC_EN_G	integer range 1 to 4 := 4

Ports
extRst	in	sl
pgpClk	out	sl
pgpRst	out	sl
stableClk	out	sl
pgpTxIn	in	Pgp2bTxInType
pgpTxOut	out	Pgp2bTxOutType
pgpRxIn	in	Pgp2bRxInType
pgpRxOut	out	Pgp2bRxOutType
pgpTxMasters	in	AxiStreamMasterArray ( 3 downto 0 )
pgpTxSlaves	out	AxiStreamSlaveArray ( 3 downto 0 )
pgpRxMasters	out	AxiStreamMasterArray ( 3 downto 0 )
pgpRxCtrl	in	AxiStreamCtrlArray ( 3 downto 0 )
gtClkP	in	sl
gtClkN	in	sl
gtTxP	out	sl
gtTxN	out	sl
gtRxP	in	sl
gtRxN	in	sl
txPreCursor	in	slv ( 4 downto 0 ) := ( others = > ' 0 ' )
txPostCursor	in	slv ( 4 downto 0 ) := ( others = > ' 0 ' )
txDiffCtrl	in	slv ( 3 downto 0 ) := " 1000 "
drpOverride	in	sl := ' 0 '
qPllRxSelect	in	slv ( 1 downto 0 ) := " 00 "
qPllTxSelect	in	slv ( 1 downto 0 ) := " 00 "
axilClk	in	sl := ' 0 '
axilRst	in	sl := ' 0 '
axilReadMaster	in	AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C
axilReadSlave	out	AxiLiteReadSlaveType
axilWriteMaster	in	AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C
axilWriteSlave	out	AxiLiteWriteSlaveType

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The documentation for this design unit was generated from the following file:

• protocols/pgp/pgp2b/gtp7/rtl/Pgp2bGtp7VarLatWrapper.vhd